Inference & Serving · core
Inference Hardware
GPUs, TPUs, NPUs, CPUs, memory bandwidth, interconnects, topology, precision support, and deployment fit.
Mental model
Inference hardware is a memory-and-interconnect system around matrix engines. Choose by model fit, precision, bandwidth, topology, power, software support, and workload shape.
How to study Inference Hardware
Begin by restating the mental model in your own words, then connect it to a concrete system you have built or operated. Name the mechanism, the constraint it addresses, and the trade-off it introduces. Use TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning, Stanford Lecture 15 — Efficient Methods and Hardware for Deep Learning (Song Han), In-Datacenter Performance Analysis of a Tensor Processing Unit (ISCA '17) to check details, but close the source before writing your explanation. Retrieval is the learning step; rereading is only preparation.
Next, compare Inference Hardware with GPU Utilization, Inference Cost & Latency Optimization. Ask what changes in correctness, latency, resource use, operability, and failure recovery. Complete Design exercise: Inference Hardware and preserve the command, input, output, and one failed attempt as evidence. Finish by explaining the idea without jargon to someone who has not studied the track.
Proof of understanding
- Explain the mechanism from first principles and identify the state it reads or changes.
- Give one situation where the concept is the right choice and one where it is not.
- Predict a realistic failure mode before running the drill, then compare the prediction with evidence.
- Connect the result to a roadmap or build artifact instead of treating the concept as isolated trivia.
Learn from primary sources
- TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning (doc)
- Stanford Lecture 15 — Efficient Methods and Hardware for Deep Learning (Song Han) (video)
- In-Datacenter Performance Analysis of a Tensor Processing Unit (ISCA '17) (paper)
- Stanford CS 217 — Hardware Accelerators for Machine Learning (doc)
- NVIDIA Hopper Architecture (doc)
Practice and explain it back
Design exercise: Inference Hardware
GPUs, TPUs, NPUs, CPUs, memory bandwidth, interconnects, topology, precision support, and deployment fit. Implement designOutline() returning non-empty values for: modelFit, memoryBandwidth, topology. Each value must name a concrete mechanism or decision.
Expected evidence: A design outline with modelFit, memoryBandwidth, topology plus an explicit failure mode or trade-off.
Open the interactive drill →Review prompts
- For single-stream LLM decoding, which hardware number predicts speed best, and why is it not peak TFLOPs?
Build evidence
Synthesize: Inference & Serving
Build a production mental model for inference engines, memory, kernels, routing, hardware, and serving economics. Produce one working system, benchmark, or evidence-backed design that integrates the path.
- Implements or precisely models the core mechanisms from all three milestones
- Includes at least one injected failure or adversarial case and demonstrates recovery
- Reports quality, latency, resource, reliability, or usability measurements relevant to the domain
- Ships a concise architecture note explaining decisions, trade-offs, and remaining risks
Prerequisites
None assigned yet.